module frequency_divisio_10Hz(
	input clk_12800Hz,
	input rst_n,
	output reg clk_10Hz
);

	reg[9:0] counter;

	always @(posedge clk_12800Hz or negedge rst_n) begin
		
		if(rst_n == 1'b0) begin
			counter <= 10'd0;
			clk_10Hz <= 1'b0;
		end
		else begin
			if(counter == 10'd639) begin //12800 / 10 = 1280 / 2 = 640 - 1 = 639
				counter <= 10'd0;
				clk_10Hz <= ~clk_10Hz;
			end
			else begin
				counter <= counter + 1;
			end
		end
		
	end
	
endmodule
